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key features 5 volt read, program, and erase ? minimizes system-level power requirements high performance ? access times as fast as 45 ns low power consumption ? 20 ma typical active read current ? 30 ma typical program/erase current ? 1 a typical cmos standby current compatible with jedec standards ? package, pinout and command-set compatible with the single-supply flash device standard ? provides superior inadvertent write protection sector erase architecture ? boot sector architecture with top boot block location ? one 16 kbyte, two 8 kbyte, one 32 kbyte and three 64k byte sectors ? a command can erase any combination of sectors ? supports full chip erase erase suspend/resume ? temporarily suspends a sector erase operation to allow data to be read from, or programmed into, any sector not being erased sector protection ? any combination of sectors may be locked to prevent program or erase operations within those sectors temporary sector unprotect ? allows changes in locked sectors (requires high voltage on reset# pin) internal erase algorithm ? automatically erases a sector, any combination of sectors, or the entire chip internal programming algorithm ? automatically programs and verifies data at a specified address fast program and erase times ? byte programming time: 7 s typical ? sector erase time: 1.0 sec typical ? chip erase time: 7 sec typical data# polling and toggle status bits ? provide software confirmation of completion of program or erase operations minimum 100,000 program/erase cycles space efficient packaging ? available in industry-standard 32-pin tsop and plcc packages revision 4.1, may 2001 general description the hy29f002t is an 2 megabit, 5 volt-only cmos flash memory organized as 262,144 (256k) bytes. the device is offered in industry- standard 32-pin tsop and plcc packages. the hy29f002t can be programmed and erased in-system with a single 5-volt v cc supply. inter- nally generated and regulated voltages are pro- vided for program and erase operations, so that the device does not require a high voltage power supply to perform those functions. the device can also be programmed in standard eprom pro- grammers. access times as fast as 55ns over the full operating voltage range of 5.0 volts 10% are offered for timing compatibility with the zero wait state requirements of high speed microprocessors. a 45ns version operating over 5.0 volts 5% is also available. to eliminate bus contention, the a[17:0] 18 ce# oe# we# 8 dq[7:0] reset# logic diagram hy29f002t 2 megabit (256k x 8), 5 volt-only, flash memory
2 rev. 4.1/may 01 hy29f002t block diagram state control we# ce# oe# command register dq[7:0] v cc detector timer erase voltage generator and sector switches program voltage generator address latch x-decoder y-decoder 2 mbit flash memory array (7 sectors) y-gating data latch i/o buffers i/o control dq[7:0] a[17:0] electronic id v cc v ss reset# hy29f002t has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device is compatible with the jedec single power-supply flash command set standard. com- mands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. device programming is performed a byte at a time by executing the four-cycle program command. this initiates an internal algorithm that automati- cally times the program pulse widths and verifies proper cell margin. the hy29f002t ? s sector erase architecture allows any number of array sectors to be erased and re- programmed without affecting the data contents of other sectors. device erasure is initiated by executing the erase command. this initiates an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. during erase cycles, the device automatically times the erase pulse widths and verifies proper cell margin. to protect data in the device from accidental or unauthorized attempts to program or erase the device while it is in the system (e.g., by a virus), the device has a sector protect function which hardware write protects selected sectors. the sector protect and unprotect features can be en- abled in a prom programmer. temporary sec- tor unprotect, which requires a high voltage, al- lows in-system erasure and code changes in pre- viously protected sectors. erase suspend enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the device is fully erased when shipped from the factory. addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by reading the dq[7] (data# polling) and dq[6] (toggle) status bits. reading data from the device is similar to reading from sram or eprom de- vices. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the host can place the device into the standby mode. power consumption is greatly reduced in this mode.
3 rev. 4.1/may 01 hy29f002t pin configurations conventions unless otherwise noted, a positive logic (active high) convention is assumed throughout this docu- ment, whereby the presence at a pin of a higher, more positive voltage (nominally 5vdc) causes assertion of the signal. a ? # ? symbol following the signal name, e.g., reset#, indicates that the sig- nal is asserted in a low state (nominally 0 volts). whenever a signal is separated into numbered bits, e.g., dq[7], dq[6], ..., dq[0], the family of bits may also be shown collectively, e.g., as dq[7:0]. the designation 0xnnnn (n = 0, 1, 2, . . . , 9, a, . . . , e, f) indicates a number expressed in hexa- decimal notation. the designation 0bxxxx indi- cates a number expressed in binary notation (x = 0, 1). tsop32 dq[6] dq[5] 28 27 dq[4] dq[3] 26 25 v ss dq[2] 24 23 dq[1] dq[0] 22 21 a[0] a[1] 20 19 a[2] a[3] 18 17 oe# a[10] 32 31 ce# dq[7] 30 29 a[14] a[17] 5 6 we# v cc 7 8 reset# a[16] 9 10 a[15] a[12] 11 12 a[7] a[6] 13 14 a[5] a[4] 15 16 a[11] a[9] 1 2 a[8] a[13] 3 4 plcc32 a[3] a[2] a[1] a[0] dq[0] a[7] a[6] a[5] a[4] a[14] a[13] 9 10 11 12 13 5 6 7 8 25 24 23 22 21 29 28 27 26 4 3 2 1 32 31 30 14 15 16 17 18 19 20 a[11] oe# a[10] ce# dq[7] a[8] a[9] v ss dq[3] dq[4] dq[5] dq[6] dq[1] dq[2] a[16] reset# v cc we# a[17] a[12] a[15]
4 rev. 4.1/may 01 hy29f002t e m a n e p y t n o i t p i r c s e d ] 0 : 7 1 [ as t u p n i . h g i h e v i t c a , s s e r d d a ) k 6 5 2 ( 4 4 1 , 2 6 2 f o e n o t c e l e s s t u p n i n e e t h g i e e s e h t s i ] 0 [ a d n a b s m e h t s i ] 7 1 [ a . s n o i t a r e p o e t i r w r o d a e r r o f y a r r a e h t n i h t i w s e t y b . b s l e h t ] 0 : 7 [ q d s t u p t u o / s t u p n i e t a t s - i r t h g i h e v i t c a , s u b a t a d d n a d a e r r o f h t a p a t a d t i b - 8 n a e d i v o r p s n i p e s e h t . . s n o i t a r e p o e t i r w # e ct u p n i . w o l e v i t c a , e l b a n e p i h c r o m o r f a t a d d a e r o t d e t r e s s a e b t s u m t u p n i s i h t e h t d n a d e t a t s - i r t s i s u b a t a d e h t , h g i h n e h w . t 2 0 0 f 9 2 y h e h t o t a t a d e t i r w . e d o m y b d n a t s e h t n i d e c a l p s i e c i v e d # e ot u p n i w o l e v i t c a , e l b a n e t u p t u o s n o i t a r e p o d a e r r o f d e t r e s s a e b t s u m t u p n i s i h t . e r a e c i v e d e h t m o r f s t u p t u o a t a d , h g i h n e h w . s n o i t a r e p o e t i r w r o f d e t a g e n d n a . e t a t s e c n a d e p m i h g i h e h t n i d e c a l p e r a s n i p s u b a t a d e h t d n a d e l b a s i d # e wt u p n i . w o l e v i t c a , e l b a n e e t i r w d n a m m o c r o s d n a m m o c f o g n i t i r w s l o r t n o c e t i r w a . s n o i t a r e p o r e h t o m r o f r e p r o a t a d m a r g o r p o t r e d r o n i s e c n e u q e s . h g i h s i # e o d n a w o l s i # e c e l i h w d e t r e s s a s i # e w n e h w e c a l p s e k a t n o i t a r e p o # t e s e rt u p n i . w o l e v i t c a , t e s e r e r a w d r a h e h t g n i t t e s e r f o d o h t e m e r a w d r a h a s e d i v o r p y l e t a i d e m m i t i , t e s e r s i e c i v e d e h t n e h w . e t a t s y a r r a d a e r e h t o t t 2 0 0 f 9 2 y h e t i r w / d a e r l l a d n a d e t a t s - i r t s i s u b a t a d e h t . s s e r g o r p n i n o i t a r e p o y n a s e t a n i m r e t , d e t r e s s a s i # t e s e r e l i h w . d e t r e s s a s i t u p n i e h t e l i h w d e r o n g i e r a s d n a m m o c . e d o m y b d n a t s e h t n i e b l l i w e c i v e d e h t v c c - - . y l p p u s r e w o p ) l a n i m o n ( t l o v - 5 v s s - - . d n u o r g l a n g i s d n a r e w o p signal descriptions memory array organization the 256 kbyte flash memory array is organized into seven blocks called sectors (s0, s1, . . . , s6). a sector is the smallest unit that can be erased and which can be protected to prevent accidental or unauthorized erasure. see the ? bus operations ? and ? command definitions ? sections of this document for additional information on these functions. table 1. hy29f002t memory array organization in the hy29f002t, four of the sectors, which com- prise the boot block , vary in size from 8 to 32 kbytes, while the remaining three sectors are uniformly sized at 64 kbytes. in this device, the boot block is located at the top of the address range. table 1 defines the sector addresses and corre- sponding address ranges for the hy29f002t. r o t c e s e z i s ) s e t y b k ( s s e r d d a r o t c e s e g n a r s s e r d d a ] 7 1 [ a ] 6 1 [ a ] 5 1 [ a ] 4 1 [ a ] 3 1 [ a 0 s4 600xxx f f f f 0 x 0 - 0 0 0 0 0 x 0 1 s4 601xxx f f f f 1 x 0 - 0 0 0 0 1 x 0 2 s4 610xxx f f f f 2 x 0 - 0 0 0 0 2 x 0 3 s2 3110xx f f f 7 3 x 0 - 0 0 0 0 3 x 0 4 s 8 11100 f f f 9 3 x 0 - 0 0 0 8 3 x 0 5 s 8 11101 f f f b 3 x 0 - 0 0 0 a 3 x 0 6 s6 1 1111x f f f f 3 x 0 - 0 0 0 c 3 x 0
5 rev. 4.1/may 01 hy29f002t bus operations device bus operations are initiated through the internal command register, which consists of sets of latches that store the commands, along with the address and data information, if any, needed to execute the specific command. the command register itself does not occupy any addressable memory location. the contents of the command register serve as inputs to an internal state ma- chine whose outputs control the operation of the device. table 2 lists the normal bus operations, the inputs and control levels they require, and the resulting outputs. certain bus operations require a high voltage on one or more device pins. those are described in table 3. read operation data is read from the hy29f002t by using stan- dard microprocessor read cycles while placing the address of the byte to be read on the device ? s address inputs, a[17:0]. as shown in table 2, the host system must drive the ce# and oe# inputs low and drive we# high for a valid read opera- tion to take place. the device outputs the speci- fied array data on dq[7:0]. the hy29f002t is automatically set for reading array data after device power-up and after a hard- ware reset to ensure that no spurious alteration of the memory content occurs during the power tran- sition. no command is necessary in this mode to obtain array data, and the device remains enabled for read accesses until the command register con- tents are altered. this device features an erase suspend mode. while in this mode, the host may read the array data from or program data into any sector of memory that is not marked for erasure. if the host attempts to read from an address within an erase- suspended sector, or while the device is perform- ing an erase or byte program operation, the de- vice outputs status data instead of array data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exceptions noted above. after completing an internal program or internal erase algorithm, the hy29f002t automatically re- turns to the read array data mode. the host must issue a hardware reset or the soft- ware reset command (see command definitions) to return a sector to the read array data mode if dq[5] goes high during a program or erase cycle, or to return the device to the read array data mode while it is in the electronic id mode. write operation certain operations, including programming data and erasing sectors of memory, require the host to write a command or command sequence to the hy29f002t. writes to the device are performed by placing the byte address on the device ? s ad- dress inputs while the data to be written is input on dq[7:0]. the host system must drive the ce# and we# pins low and drive oe# high for a valid write operation to take place. all addresses are latched on the falling edge of we# or ce#, which- ever happens later. all data is latched on the ris- ing edge of we# or ce#, whichever happens first. table 2. hy29f002t normal bus operations 1 n o i t a r e p o # e c # e o # e w # t e s e r ] 0 : 7 1 [ a ] 0 : 7 [ q d d a e rllhha n i d t u o e t i r wlhlha n i d n i e l b a s i d t u p t u olhhhxz - h g i h y b d n a t s l t t # e chxxhxz - h g i h y b d n a t s s o m c # e cv c c v 5 . 0 xxv c c v 5 . 0 xz - h g i h ) y b d n a t s l t t ( t e s e r e r a w d r a hxxxlxz - h g i h ) y b d n a t s s o m c ( t e s e r e r a w d r a hxxxv s s v 5 . 0 xz - h g i h notes: 1. l = v il , h = v ih , x = don ? t care, d out = data out, d in = data in. see dc characteristics for voltage levels.
6 rev. 4.1/may 01 hy29f002t table 3. hy29f002t bus operations requiring high voltage 1, 2 notes: 1. l = v il , h = v ih , x = don ? t care. see dc characteristics for voltage levels. 2. address bits not specified are don ? t care. 3. see text for additional information. 4. sa = sector address. see table 1. n o i t a r e p o 3 # e c # e o # e w # t e s e r ] 3 1 : 7 1 [ a ] 9 [ a ] 6 [ a ] 1 [ a ] 0 [ a ] 0 : 7 [ q d t c e t o r p r o t c e slv d i xh a s 4 v d i xxx x t c e t o r p n u r o t c e sv d i v d i xh xv d i xxx x r o t c e s y r a r o p m e t t c e t o r p n u xxx v d i x xxxx x e d o c r e r u t c a f u n a mllhhxv d i lll d a x 0 e d o c e c i v e dllhhxv d i llh 0 b x 0 r o t c e s n o i t c e t o r p n o i t a c i f i r e v d e t c e t o r p n u llh h a s 4 v d i lhl 0 0 x 0 d e t c e t o r p 1 0 x 0 the ? device commands ? section of this document provides details on the specific device commands implemented in the hy29f002t. output disable operation when the oe# input is at v ih , output data from the device is disabled and the data bus pins are placed in the high impedance state. standby operation when the system is not reading from or writing to the hy29f002t, it can place the device in the standby mode. in this mode, current consump- tion is greatly reduced, and the data bus outputs are placed in the high impedance state, indepen- dent of the oe# input. the standby mode can invoked using two methods. the device enters the ce# cmos standby mode if the ce# and reset# pins are both held at v cc 0.5v. note that this is a more restricted voltage range than v ih . if both ce# and reset# are held high, but not within v cc 0.5v, the device will be in the ce# ttl standby mode, but the standby current will be greater. the device enters the reset# cmos standby mode when the reset# pin is held at v ss 0.5v. if reset# is held low but not within v ss 0.5v, the hy29f002t will be in the reset# ttl standby mode, but the standby current will be greater. see hardware reset operation section for additional information on the reset operation. the device requires standard access time (t ce ) for read access when the device is in either of the standby modes, before it is ready to read data. if the device is deselected during erasure or pro- gramming, it continues to draw active current until the operation is completed. hardware reset operation the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for the minimum specified period, the device immediately termi- nates any operation in progress, tri-states the data bus pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. if an operation was interrupted by the as- sertion of reset#, it should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. current is reduced for the duration of the reset# pulse as described in the standby operation sec- tion above. if reset# is asserted during a program or erase operation, the internal reset operation is completed within a time of t ready (during automatic algo- rithms). the system can perform a read or write operation after waiting for a minimum of t ready or until t rh after the reset# pin returns high, which- ever is longer. if reset# is asserted when a pro- gram or erase operation is not executing, the re-
7 rev. 4.1/may 01 hy29f002t set operation is completed within a time of t rp . in this case, the host can perform a read or write operation t rh after the reset# pin returns high. the reset# pin may be tied to the system reset signal. thus, a system reset would also reset the device, enabling the system to read the boot-up firmware from the flash memory. sector protect/unprotect operations hardware sector protection can be invoked to dis- able program and erase operations in any single sector or combination of sectors. this function is typically used to protect data in the device from unauthorized or accidental attempts to program or erase the device while it is in the system (e.g., by a virus) and is implemented using program- ming equipment. sector unprotection re-enables the program and erase operations in previously protected sectors. table 1 identifies the seven sector in the top and bottom boot block versions of the hy29f002t and the address ranges that each covers. the device is shipped with all sectors unprotected. the sector protect/unprotect operations require a high voltage (v id ) on address pin a[9] and the ce# and/or oe# control pins, as detailed in table 3. when implementing these operations, note that v cc must be applied to the device before applying v id , and that v id should be removed before remov- ing v cc from the device. the flow chart in figure 1 illustrates the proce- dure for protecting sectors, and timing specifica- tions and waveforms are shown in the specifica- tions section of this document. verification of pro- tection is accomplished as described in the elec- tronic id mode section and shown in the flow chart. the procedure for sector unprotection is illustrated in the flow chart in figure 2, and timing specifica- tions and waveforms are given at the end of this document. note that to unprotect any sector, all unprotected sectors must first be protected prior to the first unprotect write cycle. sectors can also be temporarily unprotected as described in the next section. temporary sector unprotect operation this feature allows temporary unprotection of pre- viously protected sectors to allow changing the data in-system. temporary sector unprotect mode is activated by setting the reset# pin to v id . while in this mode, formerly protected sec- tors can be programmed or erased by invoking the appropriate commands (see device com- mands section). once v id is removed from re- set#, all the previously protected sectors are pro- tected again. figure 3 illustrates the algorithm. electronic id mode operation the electronic id mode provides manufacturer and device identification and sector protection verifi- cation through identifier codes output on dq[7:0]. this mode is intended primarily for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. the electronic id information can also be obtained by the host through a command se- quence, as described in the device commands section. operation in the electronic id mode requires v id on address pin a[9], with additional requirements for obtaining specific data items as listed in table 2: a read cycle at address 0xxxx00 retrieves the manufacturer code (hynix = 0xad). a read cycle at address 0xxxx01 returns the device code (hy29f002t = 0xb0). a read cycle containing a sector address (table 1) in a[17:13] and the address 0x02 in a[7:0] returns 0x01 if that sector is protected, or 0x00 if it is unprotected.
8 rev. 4.1/may 01 hy29f002t start set trycnt = 1 set a[9] = oe# = v id set address: a[17:13] = sector to protect ce# = v il reset# = v ih we# = v il wait t wpp1 a[9] = v id a[17:13] = sector to protect oe# = ce# = v il a[6] = a[0] = v il a[1] = v ih read data data = 0x01? protect another sector? yes trycnt = 25? no increment trycnt no yes device failure yes no remove v id from a[9] sector protect complete apply v cc we# = v ih figure 1. sector protect procedure
9 rev. 4.1/may 01 hy29f002t start note: all sectors must be previously protected. set: trycnt = 1 set: a[9] = ce# = oe# = v id set: reset# = v ih we# = v il wait t wpp2 set: a[9] = v id oe# = ce# = v il read data data = 0x00? nsec = 6? yes trycnt = 1000? no increment trycnt no yes device failure no yes remove v id from a[9] sector unprotect complete apply v cc set sector address: a[17:13] = sector nsec a[0] = a[6] = v il a[1] = v ih nsec = nsec + 1 set: nsec = 0 we# = v ih figure 2. sector unprotect procedure start reset# = v id (all protected sectors become unprotected) perform program or erase operations reset# = v ih (all previously protected sectors return to protected state) temporary sector unprotect complete figure 3. temporary sector unprotect device commands device operations are initiated by writing desig- nated address and data command sequences into the device. a command sequence is composed of one, two or three of the following sub-segments: an unlock cycle , a command cycle and a data cycle . table 4 summarizes the composition of the valid command sequences implemented in the hy29f002t, and these sequences are fully de- scribed in table 5 and in the sections that follow. writing incorrect address and data values or writ- ing them in the improper sequence resets the hy29f002t to the read mode. read/reset 1, 2 commands the hy29f002t automatically enters the read mode after device power-up, after the reset# input is asserted and upon the completion of cer- tain commands. read/reset commands are not required to retrieve data in these cases.
10 rev. 4.1/may 01 hy29f002t notes: 1. any number of flash array read cycles are permitted. 2. additional data cycles may follow. see text. 3. any number of electronic id read cycles are permitted. d n a m m o c e c n e u q e s s e l c y c s u b f o r e b m u n k c o l n u d n a m m o c a t a d 1 t e s e r / d a e r011 e t o n 2 t e s e r / d a e r211 e t o n m a r g o r p e t y b211 e s a r e p i h c411 e s a r e r o t c e s41) 2 e t o n ( 1 d n e p s u s e s a r e010 e m u s e r e s a r e010 d i c i n o r t c e l e213 e t o n table 4. composition of command sequences a read/reset command must be issued in order to read array data in the following cases: if the device is in the electronic id mode, a read/ reset command must be written to re- turn to the read mode. if the device was in the erase suspend mode when the device entered the electronic id mode, writing the read/re- set command returns the device to the erase suspend mode. note: when in the electronic id bus operation mode, the device returns to the read mode when v id is re- moved from the a[9] pin. the read/reset command is not required in this case. if dq[5] (exceeded time limit) goes high dur- ing a program or erase operation, writing the reset command returns the sectors to the read mode (or to the erase suspend mode if the device was in erase suspend). the read/reset command may also be used to abort certain command sequences: in a sector erase or chip erase command se- quence, the read/reset command may be written at any time before erasing actually be- gins, including, for the sector erase command, between the cycles that specify the sectors to be erased (see sector erase command de- scription). this aborts the command and re- sets the device to the read mode. once era- sure begins, however, the device ignores read/ reset commands until the operation is com- plete. in a program command sequence, the read/ reset command may be written between the sequence cycles before programming actually begins. this aborts the command and resets the device to the read mode, or to the erase suspend mode if the program command se- quence is written while the device is in the erase suspend mode. once programming begins, however, the device ignores read/re- set commands until the operation is complete. the read/reset command may be written be- tween the cycles in an electronic id command sequence to abort that command. as described above, once in the electronic id mode, the read/ reset command must be written to re- turn to the read mode. byte program command the host processor programs the device a byte at a time by issuing the program command sequence shown in table 5. the sequence begins by writ- ing two unlock cycles, followed by the program setup command and, lastly, a data cycle specify- ing the program address and data. this initiates the automatic programming algorithm, which pro- vides internally generated program pulses and verifies the programmed cell margin. the host is not required to provide further controls or timings during this operation. when the automatic pro- gramming algorithm is complete, the device re- turns to the read mode. several methods are provided to allow the host to determine the status of the programming operation, as described in the write operation status section. commands written to the device during execution of the automatic programming algorithm are ig- nored. note that a hardware reset immediately terminates the programming operation. to en- sure data integrity, the aborted program command sequence should be reinitiated once the reset operation is complete. programming is allowed in any sequence. only erase operations can convert a stored ? 0 ? to a ? 1 ? . thus, a bit cannot be programmed from a ? 0 ? back to a ? 1 ? . attempting to do so will set dq[5] to ? 1 ? , and the data# polling algorithm will indicate that the operation was not successful. a read/reset command or a hardware reset is required to exit
11 rev. 4.1/may 01 hy29f002t s e l c y c s u b 3 , 2 , 1 e c n e u q e s d n a m m o c e t i r w - e l c y c s t s r i f d n o c e s d r i h t h t r u o f h t f i f h t x i s d d a a t a d d d a a t a d d d a a t a d d d a a t a d d d a a t a d d d a a t a d 1 t e s e r / d a e r 8 , 6 1x x x0 fa rd r 2 t e s e r / t e s e r 8 , 7 35 5 5a aa a 25 55 5 50 fa rd r m a r g o r p e t y b45 5 5a aa a 25 55 5 50 aa pd p e s a r e p i h c65 5 5a aa a 25 55 5 50 85 5 5a aa a 25 55 5 50 1 e s a r e r o t c e s65 5 5a aa a 25 55 5 50 85 5 5a aa a 25 5a s0 3 d n e p s u s e s a r e 4 1x x x0 b e m u s e r e s a r e 5 1x x x0 3 c i n o r t c e l e d i 7 e d o c r e r u t c a f u n a m 35 5 5a aa a 25 55 5 50 9 0 0 xd a t 2 0 0 f 9 2 y h - e d o c e c i v e d 1 0 x0 b y f i r e v t c e t o r p p u o r g a s vt a t s table 5. hy29f002t command sequences legend: x = don ? t care pa = address of the data to be programmed ra = memory address of data to be read pd = data to be programmed at address pa rd = data read from location ra during the read operation sa = sector address of sector to be erased (see note 3 and table 1). stat = sector protect status: 0x00 = unprotected, 0x01 = protected. vsa = address of the sector to be verified (see note 3 and t able 1). notes: 1. all values are in hexadecimal. 2. all bus cycles are write operations unless otherwise noted. 3. address is a[10:0] and a[17:11] are don ? t care except as follows: ? for ra and pa, a[17:11] are the upper address bits of the byte to be read or programmed. for sa, a[17:13] are the sector address of the sector to be erased and a[12:0] are don ? t care. for vsa, a[17:13] are the address of the sector to be verified, a[7:0] = 0x02, all other address bits are don ? t care. 4. the erase suspend command is valid only during a sector erase operation. the system may read and program in non-erasing sect ors, or enter the electronic id mode, while in the erase suspend mode. 5. the erase resume command is valid only during the erase suspend mode. 6. the second bus cycle is a read cycle. 7. the fourth bus cycle is a read cycle. 8. either command sequence is valid. the command is required only to return to the read mode when the device is in the electron ic id command mode or if dq[5] goes high during a program or erase operation. it is not required for normal read operations.
12 rev. 4.1/may 01 hy29f002t start issue program command sequence: last cycle contains program address/data check programming status (see write operation status section) last word/byte done? yes no programming complete go to error recovery dq[5] error exit normal exit figure 4. programming procedure start issue chip erase command sequence check erase status (see write operation status section) chip erase complete go to error recovery dq[5] error exit normal exit this state, and a succeeding read will show that the data is still ? 0 ? . figure 4 illustrates the procedure for the program operation. chip erase command the chip erase command sequence consists of two unlock cycles, followed by the erase command, two additional unlock cycles and then the chip erase data cycle. during chip erase, all sectors of the device are erased except protected sectors. the command sequence starts the automatic erase al- gorithm, which preprograms and verifies the entire memory, except for protected sectors, for an all zero data pattern prior to electrical erase. the device then provides the required number of internally generated erase pulses and verifies cell erasure within the proper cell margins. the host system is not required to provide any controls or timings dur- ing these operations. commands written to the device during execution of the automatic erase algorithm are ignored. note that a hardware reset immediately terminates the erase operation. to ensure data integrity, the aborted chip erase command sequence should be reissued once the reset operation is complete. when the automatic erase algorithm is finished, the device returns to the read mode. several methods are provided to allow the host to deter- mine the status of the erase operation, as de- scribed in the write operation status section. figure 5 illustrates the chip erase procedure. sector erase command the sector erase command sequence consists of two unlock cycles, followed by the erase com- mand, two additional unlock cycles and then the sector erase data cycle, which specifies which sector is to be erased. as described later in this section, multiple sectors can be specified for era- sure with a single command sequence. during sector erase, all specified sectors are erased se- quentially. the data in sectors not specified for erasure, as well as the data in any protected sec- tors specified for erasure, is not affected by the sector erase operation. the sector erase command sequence starts the automatic erase algorithm, which preprograms and verifies the specified unprotected sectors for an all zero data pattern prior to electrical erase. the device then provides the required number of internally generated erase pulses and verifies cell erasure within the proper cell margins. the host system is not required to provide any controls or timings during these operations. after the sector erase data cycle (the sixth bus cycle) of the command sequence is issued, a sec- tor erase time-out of 50 s (minimum), measured from the rising edge of the final we# pulse in that bus cycle, begins. during this time, an additional sector erase data cycle, specifying the sector ad- dress of another sector to be erased, may be writ- ten into an internal sector erase buffer. this buffer figure 5. chip erase procedure
13 rev. 4.1/may 01 hy29f002t may be loaded in any sequence, and the number of sectors specified may be from one sector to all sectors. the only restriction is that the time be- tween these additional data cycles must be less than 50 s, otherwise erasure may begin before the last data cycle is accepted. to ensure that all data cycles are accepted, it is recommended that host processor interrupts be disabled during the time that the additional cycles are being issued and then be re-enabled afterwards. note: the device is capable of accepting three ways of invoking erase commands for additional sectors during the time-out window. the preferred method, described above, is the sector erase data cycle after the initial six bus cycle command sequence. how- ever, the device also accepts the following methods of specifying additional sectors during the sector erase time-out: repeat the entire six-cycle command sequence, speci- fying the additional sector in the sixth cycle. repeat the last three cycles of the six-cycle command sequence, specifying the additional sector in the third cycle. if all sectors scheduled for erasing are within pro- tected sectors, the device returns to reading ar- ray data after approximately 100 s. if at least one selected sector is not protected, the erase operation erases the unprotected sectors, and ig- start yes erase an additional sector? check erase status (see write operation status section) setup first (or next) sector address for erase operation erase complete write first five cycles of sector erase command sequence write last cycle (sa/0x30) of sector erase command sequence sector erase time-out (dq[3]) expired? no yes no go to error recovery dq[5] error exit normal exit sectors which require erasure but which were not specified in this erase cycle must be erased later using a new command sequence figure 6. sector erase procedure nores the command for the selected sectors that are protected. the system can monitor dq[3] to determine if the 50 s sector erase time-out has expired, as de- scribed in the write operation status section. if the time between additional sector erase data cycles can be insured to be less than the time- out, the system need not monitor dq[3]. any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must then rewrite the command sequence, including any additional sector erase data cycles. once the sector erase operation itself has begun, only the erase suspend command is valid. all other com- mands are ignored. as for the chip erase command, note that a hard- ware reset immediately terminates the erase op- eration. to ensure data integrity, the aborted sec- tor erase command sequence should be reissued once the reset operation is complete. when the automatic erase algorithm terminates, the device returns to the read mode. several methods are provided to allow the host to deter- mine the status of the erase operation, as de- scribed in the write operation status section.
14 rev. 4.1/may 01 hy29f002t figure 6 illustrates the sector erase procedure. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation to read data from, or program data in, any sector not being erased. the command causes the erase opera- tion to be suspended in all sectors selected for erasure. this command is valid only during the sector erase operation, including during the 50 s time-out period at the end of the initial command sequence and any subsequent sector erase data cycles, and is ignored if it is issued during chip erase or programming operations. the hy29f002t requires a maximum of 20 s to suspend the erase operation if the erase suspend command is issued during active sector erasure. however, if the command is written during the time- out, the time-out is terminated and the erase op- eration is suspended immediately. any subse- quent attempts to specify additional sectors for erasure by writing the sector erase data cycle (sa/ 0x30) will be interpreted as the erase resume command (xxx/0x30), which will cause the auto- matic erase algorithm to begin its operation. note that any other command during the time-out will reset the device to the read mode. once the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. nor- mal read and write timings and command defini- tions apply. reading at any address within erase- suspended sectors produces status data on dq[7:0]. the host can use dq[7], or dq[6] and dq[2] together, to determine if a sector is actively erasing or is erase-suspended. see ? write op- eration status ? for information on these status bits. after an erase-suspended program operation is complete, the host can initiate another program- ming operation (or read operation) within non-sus- pended sectors. the host can determine the sta- tus of a program operation during the erase-sus- pended state just as in the standard programming operation. the system must write the erase resume com- mand to exit the erase suspend mode and con- tinue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the de- vice has resumed erasing. the host may also write the electronic id com- mand sequence when the device is in the erase suspend mode. the device allows reading elec- tronic id codes even if the addresses used for the id read cycles are within erasing sectors, since the codes are not stored in the memory array. when the device exits the electronic id mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see electronic id section for more information. electronic id command the electronic id operation intended for use in programming equipment has been described pre- viously. the host processor can also be obtain the same data by using the electronic id com- mand sequence shown in table 5. this method does not require v id on any pin. the electronic id command sequence may be invoked while the device is in the read mode or the erase suspend mode, but is invalid while the device is actively programming or erasing. the electronic id command sequence is initiated by writing two unlock cycles, followed by the elec- tronic id command. the device then enters the electronic id mode, and: a read cycle at address 0xxxx00 retrieves the manufacturer code (hynix = 0xad). a read cycle at address 0xxxx01 returns the device code (0xb0). a read cycle containing a sector address in a[17:13] and the address 0x02 in a[7:0] returns 0x01 if that sector is protected, or 0x00 if it is unprotected. the host system may read at any address any number of times, without initiating another com- mand sequence. thus, for example, the host may determine the protection status for all sectors by doing successive reads at address 0x02 while changing the sector address in a[17:13] for each cycle. the system must write the reset command to exit the electronic id mode and return to the read mode, or to the erase suspend mode if the de- vice was in that mode when the command se- quence was issued.
15 rev. 4.1/may 01 hy29f002t write operation status the hy29f002t provides a number of facilities to determine the status of a program or erase op- eration. these are provided through certain bits of a status word which can be read from the de- vice during the programming and erase operations. table 6 summarizes the status indications and further detail is provided in the subsections which follow. dq[7] - data# polling the data# ( ? data bar ? ) polling bit, dq[7], indicates to the host system whether an automatic algo- rithm is in progress or completed, or whether the device is in erase suspend mode. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. the system must do a read at the program ad- dress to obtain valid programming status informa- tion on this bit. while a programming operation is in progress, the device outputs the complement of the value programmed to dq[7]. when the pro- gramming operation is complete, the device out- puts the value programmed to dq[7]. if a pro- gram operation is attempted within a protected sector, data# polling on dq[7] is active for ap- proximately 2 s, then the device returns to read- ing array data. the host must read at an address within any non- protected sector scheduled for erasure to obtain valid erase status information on dq[7]. during table 6. write and erase operation status summary notes: 1. a valid address is required when reading status information. see text for additional information. 2. dq[5] status switches to a ? 1 ? when a program or erase operation exceeds the maximum timing limit. 3. a ? 1 ? during sector erase indicates that the 50 s timeout has expired and active erasure is in progress. dq[3] is not applicable to the chip erase operation. 4. equivalent to ? no toggle ? because data is obtained in this state. 5. programming can be done only in a non-suspended sector (a sector not marked for erasure). e d o m n o i t a r e p o ] 7 [ q d 1 ] 6 [ q d ] 5 [ q d ] 3 [ q d ] 2 [ q d 1 l a m r o n s s e r g o r p n i g n i m m a r g o r p# ] 7 [ q de l g g o t1 / 0 2 a / na / n d e t e l p m o c g n i m m a r g o r pa t a da t a d 4 a t a da t a da t a d s s e r g o r p n i e s a r e0e l g g o t1 / 0 2 1 3 e l g g o t d e t e l p m o c e s a r e1a t a d 4 a t a da t a da t a d 4 e s a r e d n e p s u s r o t c e s d e d n e p s u s e s a r e n i h t i w d a e r1e l g g o t o n0a / ne l g g o t r o t c e s d e d n e p s u s e s a r e - n o n n i h t i w d a e ra t a da t a da t a da t a da t a d s s e r g o r p n i g n i m m a r g o r p 5 # ] 7 [ q de l g g o t1 / 0 2 a / na / n d e t e l p m o c g n i m m a r g o r p 5 a t a da t a d 4 a t a da t a da t a d an erase operation, data# polling produces a ? 0 ? on dq[7]. when the erase operation is complete, or if the device enters the erase suspend mode, data# polling produces a ? 1 ? on dq[7]. if all sec- tors selected for erasing are protected, data# polling on dq[7] is active for approximately 100 s, then the device returns to reading array data. if at least one selected sector is not protected, the erase operation erases the unprotected sectors, and ignores the command for the selected sec- tors that are protected. when the system detects that dq[7] has changed from the complement to true data (or ? 0 ? to ? 1 ? for erase), it should do an additional read cycle to read valid data from dq[7:0]. this is because dq[7] may change asynchronously with respect to the other data bits while output enable (oe#) is as- serted low. figure 7 illustrates the data# polling test algorithm. dq[6] - toggle bit i toggle bit i on dq[6] indicates whether an auto- matic program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the program or erase command sequence, including during the sector erase time-out. the system may use either oe# or ce# to control the read cycles.
16 rev. 4.1/may 01 hy29f002t start read dq[7:0] at valid address (note 1) dq[7] = data? no yes program/erase complete dq[5] = 1? no yes test for dq[7] = 1? for erase operation read dq[7:0] at valid address (note 1) dq[7] = data? (note 2) no yes test for dq[7] = 1? for erase operation program/erase exceeded time error notes: 1. during programming, the program address. during sector erase, an address within any non-protected sector scheduled for erasure. during chip erase, an address within any non-protected sector. 2. recheck dq[7] since it may change asynchronously at the same time as dq[5]. figure 7. data# polling test algorithm successive read cycles at any address during an automatic program algorithm operation (including programming while in erase suspend mode) cause dq[6] to toggle. dq[6] stops toggling when the operation is complete. if a program address falls within a protected sector, dq[6] toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. while the automatic erase algorithm is operating, successive read cycles at any address cause dq[6] to toggle. dq[6] stops toggling when the erase operation is complete or when the device is placed in the erase suspend mode. the host may use dq[2] to determine which sectors are erasing or erase-suspended (see below). after an erase command sequence is written, if all sectors se- lected for erasing are protected, dq[6] toggles for approximately 100 s, then returns to reading ar- ray data. if at least one selected sector is not protected, the automatic erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. dq[2] - toggle bit ii toggle bit ii, dq[2], when used with dq[6], indi- cates whether a particular sector is actively eras- ing or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. the device toggles dq[2] with each oe# or ce# read cycle. dq[2] toggles when the host reads at addresses within sectors that have been selected for erasure, but cannot distinguish whether the sector is ac- tively erasing or is erase-suspended. dq[6], by comparison, indicates whether the device is ac- tively erasing or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. figure 8 illustrates the operation of toggle bits i and ii. dq[5] - exceeded timing limits dq[5] is set to a ? 1 ? when the program or erase time has exceeded a specified internal pulse count limit. this is a failure condition that indicates that the program or erase cycle was not successfully completed. dq[5] status is valid only while dq[7] or dq[6] indicate that an automatic algorithm is in progress. the dq[5] failure condition will also be signaled if the host tries to program a ? 1 ? to a location that is previously programmed to ? 0 ? , since only an erase operation can change a ? 0 ? to a ? 1 ? . for both of these conditions, the host must issue a read/reset command to return the device to the read mode. dq[3] - sector erase timer after writing a sector erase command sequence, the host may read dq[3] to determine whether or not an erase operation has begun. when the sector erase time-out expires and the sector erase operation commences, dq[3] switches from a ? 0 ?
17 rev. 4.1/may 01 hy29f002t read dq[7:0] at valid address (note 1) dq[6] toggled? no (note 3) yes program/erase complete dq[5] = 1? no yes read dq[7:0] at valid address (note 1) dq[6] toggled? (note 2) no yes program/erase exceeded time error notes : 1. during programming, the program address. during sector erase, an address within any sector scheduled for erasure. 2. recheck dq[6] since toggling may stop at the same time as dq[5] changes from 0 to 1. 3. use this path if testing for program/erase status. 4. use this path to test whether sector is in erase suspend mode. read dq[7:0] at valid address (note 1) start read dq[7:0] dq[2] toggled? no sector being read is in erase suspend read dq[7:0] yes no (note 4) sector being read is not in erase suspend figure 8. toggle bit i and ii test algorithm to a ? 1 ? . refer to the ? sector erase command ? section for additional information. note that the sector erase timer does not apply to the chip erase command. after the initial sector erase command sequence is issued, the system should read the status on dq[7] (data# polling) or dq[6] (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq[3]. if dq[3] is a ? 1 ? , the internally controlled erase cycle has begun and all further sector erase data cycles or commands (other than erase suspend) are ignored until the erase operation is complete. if dq[3] is a ? 0 ? , the device will accept a sector erase data cycle to mark an additional sector for erasure. to ensure that the data cycles have been accepted, the system software should check the status of dq[3] prior to and following each subsequent sector erase data cycle. if dq[3] is high on the second status check, the last data cycle might not have been accepted. hardware data protection the hy29f002t provides several methods of pro- tection to prevent accidental erasure or program- ming which might otherwise be caused by spuri- ous system level signals during v cc power-up and power-down transitions, or from system noise. these methods are described in the sections that follow. command sequences commands that may alter array data require a sequence of cycles as described in table 5. this provides data protection against inadvertent writes. low v cc write inhibit to protect data during v cc power-up and power- down, the device does not accept write cycles when v cc is less than v lko (typically 3.7 volts). the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko .
18 rev. 4.1/may 01 hy29f002t write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by asserting any one of the following conditions: oe# = v il , ce# = v ih , or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power- up. sector protection additional data protection is provided by the hy29f002t ? s sector protect feature, described previously, which can be used to protect sensitive areas of the flash array from accidental or unau- thorized attempts to alter the data.
19 rev. 4.1/may 01 hy29f002t absolute maximum ratings 4 notes: 1. minimum dc voltage on input or i/o pins is ? 0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to -2.0v for periods of up to 20 ns. see figure 9. maximum dc voltage on input or i/o pins is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 10. 2. minimum dc input voltage on pins a[9], oe#, and reset# is -0.5 v. during voltage transitions, a[9], oe#, and reset# may undershoot v ss to ? 2.0 v for periods of up to 20 ns. see figure 9. maximum dc input voltage on these pins is +12.5 v which may overshoot to 13.5 v for periods up to 20 ns. 3. no more than one output at a time may be shorted to v ss . duration of the short circuit should be less than one second. 4. stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions 1 2.0 v v cc + 0.5 v v cc + 2.0 v 20 ns 20 ns 20 ns figure 9. maximum undershoot waveform figure 10. maximum overshoot waveform l o b m y s r e t e m a r a p e u l a v t i n u t g t s e r u t a r e p m e t e g a r o t s 0 5 1 + o t 5 6 -c o t s a i b d e i l p p a r e w o p h t i w e r u t a r e p m e t t n e i b m a 5 2 1 + o t 5 5 -c o v 2 n i v o t t c e p s e r h t i w n i p n o e g a t l o v s s : c c v 1 # t e s e r , # e o , ] 9 [ a 2 s n i p r e h t o l l a 1 0 . 7 + o t 0 . 2 - 5 . 2 1 + o t 0 . 2 - 0 . 7 + o t 0 . 2 - v v v i s o t n e r r u c t i u c r i c t r o h s t u p t u o 3 0 0 2a m l o b m y s r e t e m a r a p e u l a v t i n u t a : e r u t a r e p m e t g n i t a r e p o t n e i b m a0 7 + o t 0c o v c c : e g a t l o v y l p p u s g n i t a r e p o s n o i s r e v 5 4 - 2 0 0 f 9 2 y h s n o i s r e v r e h t o l l a 5 2 . 5 + o t 5 7 . 4 + 0 5 . 5 + o t 0 5 . 4 + v v 0.8 v - 0.5 v - 2.0 v 20 ns 20 ns 20 ns notes: 1. recommended operating conditions define those limits between which the functionality of the device is guaranteed.
20 rev. 4.1/may 01 hy29f002t dc characteristics ttl/nmos compatible notes: 1. includes both the dc operating current and the frequency dependent component at 6 mhz. the read component of the i cc current is typically less than 2 ma/mhz with oe# at v ih . 2. i cc active while automatic erase or automatic program algorithm is in progress. 3. i cc max measured with v cc = v cc max. 4. not 100% tested. r e t e m a r a p n o i t p i r c s e d p u t e s t s e t n i m p y t x a m t i n u i i l t n e r r u c d a o l t u p n i v n i v = s s v o t c c , v c c v = c c x a m 0 . 1 a i t i l t u p n i # t e s e r , # e o , ] 9 [ a t n e r r u c d a o l 4 v c c v = c c , x a m v 5 . 2 1 = # e o = ] 9 [ a v 5 . 2 1 = # t e s e r 0 5a i o l t n e r r u c e g a k a e l t u p t u o v t u o v = s s v o t c c , v c c v = c c x a m 0 . 1 a i 1 c c v c c t n e r r u c d a e r e v i t c a 3 , 1 v = # e c l i v = # e o , h i 0 20 3a m i 2 c c v c c t n e r r u c e t i r w e v i t c a 4 , 3 , 2 v = # e c l i v = # e o , h i 0 30 4a m i 3 c c v c c d e l l o r t n o c # e c t n e r r u c y b d n a t s l t t 3 v = # e o = # e c h i v = # t e s e r h i 4 . 00 . 1a m i 4 c c v c c d e l l o r t n o c # t e s e r t n e r r u c y b d n a t s l t t 3 v = # t e s e r l i 4 . 00 . 1a m v l i e g a t l o v w o l t u p n i5 . 0 -8 . 0v v h i e g a t l o v h g i h t u p n i0 . 2v c c 5 . 0 +v v d i d n a d i c i n o r t c e l e r o f e g a t l o v t c e t o r p n u r o t c e s y r a r o p m e t v c c v 0 . 5 =5 . 1 15 . 2 1v v l o e g a t l o v w o l t u p t u o v c c v = c c , n i m i l o a m 0 . 2 1 = 5 4 . 0v v h o e g a t l o v h g i h t u p t u o v c c v = c c , n i m i h o a m 5 . 2 - = 4 . 2v v o k l v w o l c c e g a t l o v t u o k c o l 3 2 . 32 . 4v
21 rev. 4.1/may 01 hy29f002t dc characteristics cmos compatible notes: 1. includes both the dc operating current and the frequency dependent component at 6 mhz. the read component of the i cc current is typically less than 2 ma/mhz with oe# at v ih . 2. i cc active while automatic erase or automatic program algorithm is in progress. 3. i cc max measured with v cc = v cc max. 4. not 100% tested. r e t e m a r a p n o i t p i r c s e d p u t e s t s e t n i m p y t x a m t i n u i i l t n e r r u c d a o l t u p n i v n i v = s s v o t c c , v c c v = c c x a m 0 . 1 a i t i l t u p n i # t e s e r , # e o , ] 9 [ a t n e r r u c d a o l 4 v c c v = c c , x a m v 5 . 2 1 = # e o = ] 9 [ a v 5 . 2 1 = # t e s e r 0 5a i o l t n e r r u c e g a k a e l t u p t u o v t u o v = s s v o t c c , v c c v = c c x a m 0 . 1 a i 1 c c v c c t n e r r u c d a e r e v i t c a 3 , 1 v = # e c l i v = # e o , h i 0 20 3a m i 2 c c v c c t n e r r u c e t i r w e v i t c a 4 , 3 , 2 v = # e c l i v = # e o , h i 0 30 4a m i 3 c c v c c d e l l o r t n o c # e c t n e r r u c y b d n a t s s o m c 3 v = # e c c c v 5 . 0 v = # t e s e r c c v 5 . 0 15a i 4 c c v c c d e l l o r t n o c # t e s e r t n e r r u c y b d n a t s s o m c 3 v = # t e s e r s s v 5 . 015a v l i e g a t l o v w o l t u p n i5 . 0 -8 . 0v v h i e g a t l o v h g i h t u p n iv x 7 . 0 c c v c c 3 . 0 +v v d i d n a d i c i n o r t c e l e r o f e g a t l o v t c e t o r p n u r o t c e s y r a r o p m e t v c c v 0 . 5 =5 . 1 15 . 2 1v v l o e g a t l o v w o l t u p t u o v c c v = c c , n i m i l o a m 0 . 2 1 = 5 4 . 0v v h o e g a t l o v h g i h t u p t u o v c c v = c c , n i m i h o a m 5 . 2 - = x 5 8 . 0 v c c v v c c v = c c , n i m i h o 0 0 1 - =a v c c 4 . 0 -v v o k l v w o l c c e g a t l o v t u o k c o l 3 2 . 32 . 4v key to switching waveforms m r o f e v a w s t u p n i s t u p t u o y d a e t s l o t h m o r f g n i g n a h c h o t l m o r f g n i g n a h c d e t t i m r e p e g n a h c y n a , e r a c t ' n o dn w o n k n u e t a t s , g n i g n a h c y l p p a t o n s e o d e t a t s e c n a d e p m i h g i h s i e n i l r e t n e c ) z h g i h (
22 rev. 4.1/may 01 hy29f002t test conditions table 7. test specifications figure 11. test setup measurement level 1.5 v output i nput 1.5 v 0.0 v 3.0 v hy29f002t-45, -55 versions measurement levels output input 0.45 v 2.4 v 0.8 v 2.0 v 0.8 v 2.0 v hy29f002t-70, -90 versions figure 12. input waveforms and measurement levels t s e t n o i t i d n o c 5 4 - 5 5 - 0 7 - 0 9 - t i n u d a o l t u p t u oe t a g l t t 1 c ( e c n a t i c a p a c d a o l t u p t u o l )0 30 0 1f p s e m i t l l a f d n a e s i r t u p n i50 2s n l e v e l w o l l a n g i s t u p n i0 . 05 4 . 0v l e v e l h g i h l a n g i s t u p n i0 . 34 . 2v t n e m e r u s a e m g n i m i t w o l l e v e l l a n g i s 5 . 18 . 0v t n e m e r u s a e m g n i m i t h g i h l e v e l l a n g i s 5 . 10 . 2v 6.2 kohm c l 2.7 kohm + 5v device under test all diodes are 1n3064 or equivalent
23 rev. 4.1/may 01 hy29f002t ac characteristics read operations notes: 1. not 100% tested. 2. see figure 11 and table 7 for test conditions. figure 13. read operation timings r e t e m a r a p n o i t p i r c s e d p u t e s t s e t n o i t p o d e e p s t i n u c e d e j d t s 5 4 - 5 5 - 0 7 - 0 9 - t v a v a t c r ) 1 e t o n ( e m i t e l c y c d a e rn i m5 45 50 70 9s n t v q v a t c c a y a l e d t u p t u o o t s s e r d d a v = # e c l i v = # e o l i x a m5 45 50 70 9s n t v q l e t e c y a l e d t u p t u o o t e l b a n e p i h cv = # e o l i x a m5 45 50 70 9s n t z q h e t f d ) 1 e t o n ( z h g i h t u p t u o o t e l b a n e p i h cx a m5 15 10 20 2s n t v q l g t e o y a l e d t u p t u o o t e l b a n e t u p t u ov = # e c l i x a m5 25 20 35 3s n t z q h g t f d ) 1 e t o n ( z h g i h t u p t u o o t e l b a n e t u p t u ox a m5 15 10 20 2s n t h e o e l b a n e t u p t u o ) 1 e t o n ( e m i t d l o h d a e rn i m0s n d n a e l g g o t g n i l l o p # a t a d n i m0 1s n t x q x a t h o # e c , s e s s e r d d a m o r f e m i t d l o h t u p t u o ) 1 e t o n ( t s r i f s r u c c o r e v e h c i h w , # e o r o n i m0s n addresses stable t rc t acc output valid t oe t ce t oeh t oh t df reset# outputs we# oe# ce# addresses
24 rev. 4.1/may 01 hy29f002t ac characteristics hardware reset (reset#) notes: 1. not 100% tested. 2. see figure 11 and table 7 for test conditions. figure 14. reset# timings r e t e m a r a p n o i t p i r c s e d p u t e s t s e t n o i t p o d e e p s t i n u c e d e j d t s 5 4 - 5 5 - 0 7 - 0 9 - t y d a e r c i t a m o t u a g n i r u d ( w o l n i p # t e s e r e t o n e e s ( e t i r w r o d a e r o t ) s m h t i r o g l a ) 1 x a m0 2s t y d a e r c i t a m o t u a g n i r u d t o n ( w o l n i p # t e s e r e t o n e e s ( e t i r w r o d a e r o t ) s m h t i r o g l a ) 1 x a m0 0 5s n t p r h t d i w e s l u p # t e s e rn i m0 0 5s n t h r e e s ( d a e r e r o f e b e m i t h g i h # t e s e r ) 1 e t o n n i m0 5s n reset timings not during automatic algorithms reset timings during automatic algorithms t rp ce#, oe# reset# t ready t rh t rp t ready ce#, oe# reset# t rh
25 rev. 4.1/may 01 hy29f002t ac characteristics program and erase operations notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25 c, v cc = 5.0 volts, 100,000 cycles. in addition, programming typicals assume a checkerboard pattern. maximum program and erase times are under worst case condi- tions of 90 c, v cc = 4.5 volts (4.75 volts for 45 ns version), 100,000 cycles. 3. excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program command. see table 5 for further information on command sequences. 4. excludes 0x00 programming prior to erasure. in the preprogramming step of the automatic erase algorithm, all bytes are programmed to 0x00 before erasure. 5. the typical chip programming time is considerably less than the maximum chip programming time listed since most bytes program faster than the maximum programming times specified. the device sets dq[5] = 1 only if the maximum byte program time specified is exceeded. see write operation status section for additional information. r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 5 4 - 5 5 - 0 7 - 0 9 - t v a v a t c w ) 1 e t o n ( e m i t e l c y c e t i r wn i m5 45 50 70 9s n t l w v a t s a e m i t p u t e s s s e r d d an i m0 s n t x a l w t h a e m i t d l o h s s e r d d an i m0 45 45 45 4s n t h w v d t s d e m i t p u t e s a t a dn i m5 25 20 35 4s n t x d h w t h d e m i t d l o h a t a dn i m0 s n t l w h g t l w h g e t i r w e r o f e b e m i t y r e v o c e r d a e rn i m0 s n t l w l e t s c e m i t p u t e s # e cn i m0 s n t h e h w t h c e m i t d l o h # e cn i m0 s n t h w l w t p w h t d i w e s l u p e t i r wn i m0 30 35 35 4s n t l w h w t h p w h g i h h t d i w e s l u p e t i r wn i m0 2s n t 1 h w h w t 1 h w h w ) 3 , 2 , 1 s e t o n ( n o i t a r e p o g n i m m a r g o r p e t y b p y t7s x a m0 0 3s ) 5 , 3 , 2 , 1 s e t o n ( n o i t a r e p o g n i m m a r g o r p p i h c p y t8 . 1c e s x a m4 . 5c e s t 2 h w h w t 2 h w h w ) 4 , 2 , 1 s e t o n ( n o i t a r e p o e s a r e r o t c e s p y t1c e s x a m8 c e s t 3 h w h w t 3 h w h w ) 4 , 2 , 1 s e t o n ( n o i t a r e p o e s a r e p i h c p y t7 c e s x a m5 5c e s e c n a r u d n e e l c y c m a r g o r p d n a e s a r e p y t0 0 0 , 0 0 0 , 1s e l c y c n i m0 0 0 , 0 0 1s e l c y c t s c v v c c e m i t p u t e sn i m0 5s
26 rev. 4.1/may 01 hy29f002t ac characteristics notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. figure 15. program operation timings addresses ce# t wc 0x555 pa pa pa oe# t as t ah t wph t wp t ghwl t cs we# data t ds t dh 0xa0 pd status t whwh1 t vcs v cc program command sequence (last two cycles) read status data (last two cycles) d out t ch
27 rev. 4.1/may 01 hy29f002t ac characteristics notes: 1. sa =sector address (for sector erase), va = valid address for reading status data (see write operation status section), d out is the true data at the read address.(0xff after an erase operation). 2. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. figure 16. sector/chip erase operation timings addresses ce# t wc 0x2aa va va sa oe# t as t ah t wph t wp t ghwl t cs t ch we# data t ds t dh 0x55 0x30 status d out t whwh2 or t whwh3 t vcs v cc erase command sequence (last two cycles) read status data (last two cycles) 0x555 for chip erase 0x10 for chip erase
28 rev. 4.1/may 01 hy29f002t ac characteristics notes: 1. va = valid address for reading data# polling status data (see write operation status section). 2. illustration shows first status cycle after command sequence, last status read cycle and array data read cycle. figure 17. data# polling timings (during automatic algorithms) notes: 1. va = valid address for reading toggle bits (dq[2], dq[6]) status data (see write operation status section). 2. illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle. figure 18. toggle polling timings (during automatic algorithms) t ch t oe t ce t rc complement complement true valid data status data status data true valid data dq[6:0] dq[7] we# oe# ce# addresses va va va t acc t oeh t oh t df t ch t oe t ce t rc valid status valid status valid status dq[6], [2] we# oe# ce# addresses va va va t oeh t oh t df va (second read) (first read) (stops toggling) valid data t acc
29 rev. 4.1/may 01 hy29f002t ac characteristics notes: 1. the system may use ce# or oe# to toggle dq[2] and dq[6]. dq[2] toggles only when read at an address within an erase-suspended sector. figure 19. dq[2] and dq[6] operation sector protect and unprotect, temporary sector unprotect notes: 1. not 100% tested. r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 5 4 - 5 5 - 0 7 - 0 9 - t t s e m i t p u t e s e g a t l o vn i m0 5s t p s r r o f e m i t p u t e s # t e s e r t c e t o r p n u p u o r g r o t c e s y r a r o p m e t n i m4 s t e c y a l e d t u p t u o o t e l b a n e p i h cx a m5 45 50 70 9s n t e o y a l e d t u p t u o o t e l b a n e t u p t u ox a m5 25 20 35 3s n t r d i v r o f e m i t n o i t i s n a r t e g a t l o v ) 1 e t o n ( t c e t o r p n u p u o r g r o t c e s y r a r o p m e t n i m0 0 5s n t t h l v r o f e m i t n o i t i s n a r t e g a t l o v ) 1 e t o n ( t c e t o r p n u d n a t c e t o r p p u o r g r o t c e s n i m4 s t 1 p p w t c e t o r p p u o r g r o t c e s r o f h t d i w e s l u p e t i r wn i m0 0 1s t 2 p p w t c e t o r p n u p u o r g r o t c e s r o f h t d i w e s l u p e t i r wn i m0 0 1s m t p s e o ) 1 e t o n ( e v i t c a # e w o t e m i t p u t e s # e on i m4 s t p s c ) 1 e t o n ( e v i t c a # e w o t e m i t p u t e s # e cn i m4 s erase complete we# dq[6] dq[2] enter automatic erase erase erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase suspend
30 rev. 4.1/may 01 hy29f002t ac characteristics figure 20. sector protect timings t st v cc reset# data ce# we# oe# a[9] a[6] a[1] a[0] a[17:13] v id v id sa x sa y 0x01 t vlht t vlht t vlht t wpp1 t vlht t st sector protect cycle protect verify cycle t st t oe t st t oesp
31 rev. 4.1/may 01 hy29f002t ac characteristics figure 21. sector unprotect timings v cc reset# data ce# we# oe# a[9] a[6] a[1] a[0] a[17:13] v id sa 0 sa 1 0x00 t vlht t oesp t wpp2 t st t oe sector unprotect cycle unprotect verify cycle t vlht v id v id t ce t csp t st t st
32 rev. 4.1/may 01 hy29f002t ac characteristics figure 22. temporary sector unprotect timings t vidr we# ce# reset# v id 0 or 5v t rsp t vidr 0 or 5v
33 rev. 4.1/may 01 hy29f002t ac characteristics alternate ce# controlled erase/program operations notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25 c, v cc = 5.0 volts, 100,000 cycles. in addition, programming typicals assume a checkerboard pattern. maximum program and erase times are under worst case condi- tions of 90 c, v cc = 4.5 volts (4.75 volts for 55 ns version), 100,000 cycles. 3. excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program command. see table 5 for further information on command sequences. 4. excludes 0x00 programming prior to erasure. in the preprogramming step of the automatic erase algorithm, all bytes are programmed to 0x00 before erasure. 5. the typical chip programming time is considerably less than the maximum chip programming time listed since most bytes program faster than the maximum programming times specified. the device sets dq[5] = 1 only if the maximum byte program time specified is exceeded. see write operation status section for additional information. r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 5 4 - 5 5 - 0 7 - 0 9 - t v a v a t c w ) 1 e t o n ( e m i t e l c y c e t i r wn i m5 45 50 70 9s n t l w v a t s a e m i t p u t e s s s e r d d an i m0 s n t x a l w t h a e m i t d l o h s s e r d d an i m0 45 45 45 4s n t h w v d t s d e m i t p u t e s a t a dn i m5 25 20 35 4s n t x d h w t h d e m i t d l o h a t a dn i m0 s n t l e h g t l e h g e t i r w e r o f e b e m i t y r e v o c e r d a e rn i m0 s n t l e l w t s w e m i t p u t e s # e wn i m0 s n t h w h e t h w e m i t d l o h # e wn i m0 s n t h e l e t p c h t d i w e s l u p # e cn i m0 30 35 35 4s n t l e h e t h p c h g i h h t d i w e s l u p # e cn i m0 2s n t 1 h w h w t 1 h w h w ) 3 , 2 , 1 s e t o n ( n o i t a r e p o g n i m m a r g o r p e t y b p y t7s x a m0 0 3s ) 5 , 3 , 2 , 1 s e t o n ( n o i t a r e p o g n i m m a r g o r p p i h c p y t8 . 1c e s x a m4 . 5c e s t 2 h w h w t 2 h w h w ) 4 , 2 , 1 s e t o n ( n o i t a r e p o e s a r e r o t c e s p y t1c e s x a m8 c e s t 3 h w h w t 3 h w h w ) 4 , 2 , 1 s e t o n ( n o i t a r e p o e s a r e p i h c p y t7 c e s x a m5 5c e s e c n a r u d n e e l c y c m a r g o r p d n a e s a r e p y t0 0 0 , 0 0 0 , 1s e l c y c n i m0 0 0 , 0 0 1s e l c y c
34 rev. 4.1/may 01 hy29f002t ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading program or erase status (see write operation status section), d out = array data read at va. 2. illustration shows the last two cycles of the program or erase command sequence and the last status read cycle. 3. word mode addressing shown. 4. reset# shown only to illustrate t rh measurement references. it cannot occur as shown during a valid command sequence. figure 23. alternate ce# controlled write operation timings 0x555 for program 0x2aa for erase pa for program sa for sector erase 0x555 for chip erase t ws t rh t wh ce# oe# addresses t wc va t as t ah we# data t ds status d out t whwh1 or t whwh2 or t whwh3 t dh 0xa0 for program 0x55 for erase pd for program 0x30 for sector erase 0x10 for chip erase reset# t cp t cph t ghel
35 rev. 4.1/may 01 hy29f002t latchup characteristics notes: 1. includes all pins except v cc . test conditions: v cc = 5.0v, one pin at a time. tsop pin capacitance plcc and pdip pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions: t a = 25 o c, f = 1.0 mhz. notes: 1. sampled, not 100% tested. 2. test conditions: t a = 25 o c, f = 1.0 mhz. data retention n o i t p i r c s e d m u m i n i m m u m i x a m t i n u v o t t c e p s e r h t i w e g a t l o v t u p n i s s s n i p o / i t p e c x e s n i p l l a n o ) # t e s e r d n a # e o , ] 9 [ a g n i d u l c n i ( 0 . 1 -5 . 2 1v v o t t c e p s e r h t i w e g a t l o v t u p n i s s s n i p o / i l l a n o0 . 1 -v c c 0 . 1 +v v c c t n e r r u c0 0 1 -0 0 1a m l o b m y s r e t e m a r a p p u t e s t s e t p y t x a m t i n u c n i e c n a t i c a p a c t u p n iv n i 0 =65 . 7f p c t u o e c n a t i c a p a c t u p t u ov t u o 0 =5 . 82 1f p c 2 n i e c n a t i c a p a c n i p l o r t n o cv n i 0 =5 . 79 f p l o b m y s r e t e m a r a p p u t e s t s e t p y t x a m t i n u c n i e c n a t i c a p a c t u p n iv n i 0 =46f p c t u o e c n a t i c a p a c t u p t u ov t u o 0 =82 1f p c 2 n i e c n a t i c a p a c n i p l o r t n o cv n i 0 =80 1f p r e t e m a r a p s n o i t i d n o c t s e t m u m i n i m t i n u e m i t n o i t n e t e r a t a d n r e t t a p m u m i n i m c o 0 5 10 1s r a e y c o 5 2 10 2s r a e y
36 rev. 4.1/may 01 hy29f002t package drawings physical dimensions tsop32 - 32-pin thin small outline package (measurements in millimeters) plcc32 - 32-pin plastic leaded chip carrier (measurements in inches) 18.30 18.50 pin 1 i.d. 7.90 8.10 .015 .060 0.10 0.21 0.25mm (0.0098") bsc 1.20 max 1 17 32 19.80 20.20 0.08 0.20 0 5 o o 0.95 1.05 0.50 bsc 0.05 0.15 16 side view .447 .453 top view .050 ref. pin 1 i.d. .485 .495 .547 .553 .585 .595 . 026 .032 .042 .056 seating plane .530 .009 .015 .080 .095 .125 .140 .013 .021 .400 ref .490
37 rev. 4.1/may 01 hy29f002t 2 0 0 f 9 2 y h xx-xxx s n o i t c u r t s n i l a i c e p s e g n a r e r u t a r e p m e t = k n a l b) c 0 7 + o t 0 ( l a i c r e m m o c n o i t p o d e e p s = 5 4 = 5 5 = 0 7 = 0 9 s n 5 4 s n 5 5 s n 0 7 s n 0 9 e p y t e g a k c a p = c = t ) c c l p ( r e i r r a c p i h c d e d a e l c i t s a l p n i p - 2 3 ) p o s t ( e g a k c a p e n i l t u o l l a m s n i h t n i p - 2 3 n o i t a c o l k c o l b t o o b = tk c o l b t o o b p o t r e b m u n e c i v e d = 2 0 0 f 9 2 y hr o t c e s y l n o - t l o v 5 s o m c ) 8 x k 6 5 2 ( t i b a g e m 2 y r o m e m h s a l f e s a r e ordering information hynix products are available in several speeds, packages and operating temperature ranges. the ordering part number is formed by combining a number of fields, as indicated below. refer to the ? valid combinations ? table, which lists the configurations that are planned to be supported in volume. please contact your local hynix representative or distributor to confirm current availability of specific configura- tions and to determine if additional configurations have been released. valid combinations d e e p s d n a e g a k c a p p o s t c c l p e r u t a r e p m e t s n 5 4 s n 5 5 s n 0 7 s n 0 9 s n 5 4 s n 5 5 s n 0 7 s n 0 9 l a i c r e m m o c5 4 - t5 5 - t0 7 - t0 9 - t5 4 - c5 5 - c0 7 - c0 9 - c note: 1. the complete part number is formed by appending the boot block location code and the suffix shown in the table above to the device number. for example, the part number for a 90 ns, commercial temperature range device in the tsop package with the top boot block is hy29f002tt-90 .
38 rev. 4.1/may 01 hy29f002t important notice ? 2001 by hynix semiconductor america. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of hynix semiconductor inc. or hynix semiconductor america (collec- tively ? hynix ? ). the information in this document is subject to change without notice. hynix shall not be responsible for any errors that may appear in this document and makes no commitment to update or keep current the information contained in this document. hynix advises its customers to obtain the latest version of the device specification to verify, before placing orders, that the information being relied upon by the customer is current. devices sold by hynix are covered by warranty and patent in- demnification provisions appearing in hynix terms and condi- tions of sale only. hynix makes no warranty, express, statu- tory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. hynix makes no war- ranty of merchantability or fitness for any purpose. hynix ? s products are not authorized for use as critical compo- nents in life support devices or systems unless a specific writ- ten agreement pertaining to such intended use is executed between the customer and hynix prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustain life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. d r o c e r n o i s i v e r . v e r e t a d s l i a t e d 1 . 41 0 / 5 . t a m r o f x i n y h o t e g n a h c n o i t p o e g a k c a p p i d p d n a n o i t p o k c o l b t o o b m o t t o b d e v o m e r memory sales and marketing division flash memory business unit hynix semiconductor inc. hynix semiconductor america inc. 10 fl., hynix youngdong building 3101 north first street 89, daechi-dong san jose, ca 95134 kangnam-gu usa seoul, korea telephone: (408) 232-8800 telephone: +82-2-580-5000 fax: (408) 232-8805 fax: +82-2-3459-3990 http://www.us.hynix.com http://www.hynix.com

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